library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity debounced_input is
	generic ( 
		BounceCount: natural range 1 to 100 := 100;
		NumInputs: natural range 1 to 32 := 8
	);
	port (
		Clock: in std_logic;
		Inputs: in std_logic_vector(NumInputs-1 downto 0);
		Output: out std_logic_vector(NumInputs-1 downto 0)
	);
end entity debounced_input;

architecture str of debounced_input is
begin
	single_input: for x in NumInputs-1 downto 0 generate
		db_input: entity work.debouncer(beh)
			generic map (BounceCount => BounceCount)
			port map (
				Clock=> Clock, 
				Orig => Inputs(x), 
				Debounced => Output(x)
			);
	end generate single_input;
end architecture str;